1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device with a vertical channel transistor and a method for fabricating the same.
2. Description of the Related Art
Most semiconductor devices include transistors. For example, in a memory device such as a DRAM, a memory cell includes a cell transistor such as a MOSFET. In general, in a MOSFET, source/drain regions are formed in a semiconductor substrate, and by this fact, a planar channel is formed between the source region and the drain region. Such a general MOSFET is referred to as a ‘planar channel transistor’.
As improvements in the degree of integration and performance are continuously required in a memory device, a MOSFET fabrication technology has a physical limit. For instance, as the size of a memory cell decreases, the size of a MOSFET decreases, and due to this fact, the channel length of the MOSFET cannot help but decrease. If the channel length of a MOSFET decreases, the characteristics of a memory device are likely to deteriorate due to various problems caused in that data retention characteristics deteriorate.
In consideration of these problems, a vertical channel transistor has been suggested. The vertical channel transistor (VCT) has a source region and a drain region which are formed in top and bottom portions of a pillar. The pillar serves as a channel, and a vertical gate electrode is formed on the sidewall of the pillar.
The vertical gate electrode is formed as an all-around gate structure or a double gate structure.
However, as the critical dimension decreases to 20 nm or below due to high integration, since a gap between pillars is narrow, a gate electrode cannot help but be formed thin. If the gate electrode is formed thin, resistance is likely to increase.
Also, since the gap between pillars is narrow, if electrodes are deposited to be thicker than a predetermined thickness, it is difficult to separate electrodes. If an over-etching process is performed to separate the electrodes, an underlying structure is likely to be etched and attacked in a region with a wide gap (for example, a pad region).